1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a thin film transistor (hereinafter referred to as TFT) with a GOLD (abbreviated form of xe2x80x9cgate-overlapped-LDDxe2x80x9d) structure and a method of manufacturing the same. Note that the semiconductor device in this specification indicates semiconductor devices in general the circuit of which is configured by semiconductor devices including a TFT with a GOLD structure. For example, semiconductor display devices such as an active matrix liquid crystal display device and an organic EL (abbreviated form of xe2x80x9celectro-luminescencexe2x80x9d) display device are included in the category of the semiconductor device.
2. Description of the Related Art
In semiconductor display devices, such as an active matrix liquid crystal display device and an organic EL display device, the circuit of which is configured by TFTs on a transparent insulating substrate such as a glass substrate, a polycrystalline silicon TFT having a high field-effect mobility has attracted attention. A polycrystalline silicon film applied to the polycrystalline silicon TFT has a higher field-effect mobility of an electron or hole than a conventional amorphous silicon film, and thus has an advantage that integration of not only a pixel transistor but also a driver circuit as a peripheral circuit can be realized. Therefore, each company has been advancing the development of an active matrix semiconductor display device the circuit of which is configured by polycrystalline silicon TFTs.
In the polycrystalline silicon TFT, it has a high field-effect mobility, but on the other hand, there is observed deterioration phenomena such as lowering of the field-effect mobility or an ON current (current that flows in an ON state) and increase in an OFF current (current that flows in an OFF state) when the polycrystalline silicon TFT is continuously driven. These have been problems in terms of reliability. The deterioration phenomenon is called a hot carrier phenomenon, and is known to be caused by hot carriers generated due to a high electric field in the vicinity of a drain.
The hot carrier phenomenon is one first discovered in a MOS (abbreviated form of xe2x80x9cmetal oxide semiconductorxe2x80x9d) transistor which is manufactured on a semiconductor substrate, and it has been found that the cause of the phenomenon is the high electric field in the vicinity of a drain. Various basic examinations have been made for measures against hot carriers. The MOS transistor with a design rule of 1.5 xcexcm or less adopts an LDD (abbreviated form of xe2x80x9clightly doped drainxe2x80x9d) structure. In the LDD structure, an n-type or p-type low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region) is formed in a drain end portion by utilizing a gate side wall that is comprised of an insulating film, and a gradient is imparted to an impurity concentration of a drain junction, thereby relaxing an electric field concentration in the vicinity of a drain. Here, an n-type low concentration impurity region and an n-type high concentration impurity region are respectively called an nxe2x88x92 region and an n+ region, and a p-type low concentration impurity region and a p-type high concentration impurity region are respectively called a pxe2x88x92 region and a p+ region.
However, in the LDD structure, the resistance of the low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region) is large while a drain withstand voltage is improved much compared with a single drain structure. Thus, the LDD structure has a defect that a drain current decreases. Further, there has been the problem of a deterioration mode peculiar to the LDD in which: a high electric field region exists just under the side wall; impact ionization becomes maximum there; hot electrons are implanted into the side wall; and thus, the low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region) is depleted, and the resistance is further increased. The above-mentioned problem has been tangible along with the reduction of a channel length. Thus, as to the MOS transistor with a design rule of 0.5 xcexcm or less, the GOLD structure is developed in which a low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region) is formed so as to overlap with an end portion of a gate electrode as a structure for overcoming the above-mentioned problem, and the application of the structure to mass production has been advancing.
Under the above-mentioned background, as to the polycrystalline silicon TFT manufactured on a transparent insulating substrate such as a glass substrate as well, the development of the LDD structure or GOLD structure has been progressing with the purpose of relaxing a high electric field in the vicinity of a drain, similar to the MOS transistor. The LDD structure is such that an n-type or p-type low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region) that functions as an electric field relaxation region is formed in a semiconductor layer comprised of a polycrystalline silicon film corresponding to the outside of a gate electrode, and a high concentration impurity region (n+ region or p+ region) with the same conductivity as a source region or drain region is formed outside thereof. The LDD structure concerned has an advantage that an OFF current is small and a disadvantage that a hot carrier suppression effect due to relaxation of an electric field in the vicinity of a drain is small. On the other hand, in the GOLD structure, a low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region) is formed so as to overlap with an end portion of a gate electrode. Thus, the GOLD structure has an advantage that a hot carrier suppression effect is large and a disadvantage that an OFF current increases, in comparison with the LDD structure.
As described above, each of the LDD structure and the GOLD structure has good points and bad points. Thus, in the actual semiconductor display device, from the viewpoint of quality improvement of the semiconductor display device, there is examined the effective combination in circuit configuration of a low OFF current characteristic of the LDD structure and a high hot carrier resistance of the GOLD structure. Specifically, in the case of a pixel TFT in a pixel region, the gate structure is preferable in which importance is placed on reduction in an OFF current value rather than high reliability to a hot carrier, and thus, the LDD structure having a low OFF current characteristic is suitable. On the other hand, in the case of a peripheral circuit consisting of a driver circuit, the gate structure is preferable in which importance is placed on high reliability to a hot carrier rather than a low OFF current characteristic, and thus, the GOLD structure having high hot carrier resistance is suitable. Therefore, the recent semiconductor display device the circuit of which is configured by a polycrystalline silicon TFT has a tendency that a pixel TFT in a pixel region is comprised of an LDD structure TFT, and a peripheral circuit is comprised of a GOLD structure TFT.
Note that, as to a known example on an n-channel polycrystalline silicon GOLD structure TFT, the structure and basic characteristics of the n-channel GOLD structure TFT are disclosed in Mutsuko Hatano, Hajime Akimoto, and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997. In the structure of the GOLD structure TFT examined here, a gate electrode and a side wall for LDD are formed of polycrystalline silicon, an n-type low concentration impurity region (nxe2x88x92 region) that functions as an electric filed relaxation region is formed in an active layer (formed of polycrystalline silicon) just under the side wall for LDD, and a high concentration impurity region (n+ region) with the same conductivity which functions as a source region or drain region is formed outside thereof. As to the basic characteristics, a large drain current is obtained together with relaxation of a drain electric field, and a large suppression effect against a drain-avalanche-hot-carrier is obtained in comparison with the general LDD structure TFT.
Further, as to another example on the GOLD structure TFT, there are disclosed in JP 7-202210A, xe2x80x9ca thin film transistor with an LDD structure which is characterized in that a gate electrode takes a structure of two layers having different widths, the upper layer of which has a smaller width than that of the lower layerxe2x80x9d and xe2x80x9ca method of manufacturing a thin film transistor with an LDD structure which is characterized in that: there is formed a gate electrode with a structure of two layers having different widths, the upper layer of which has a smaller width than that of the lower layer; and then, ions are implanted in a region that serves as a source or a drain using the gate electrode as a maskxe2x80x9d. In JP 7-202210A concerned, there is described that xe2x80x9can acceleration voltage and an ion implantation amount at the time of ion implantation are appropriately selected, whereby an n+ region (or p+ region) in a region with no gate electrode, an nxe2x88x92 region (or pxe2x88x92 region) in a region only with a layer of a gate electrode, and an intrinsic (state with no ion implantation) region in a region with two layers of a gate electrode are simultaneously formed at the time of ion implantationxe2x80x9d. There is provided a structure in which an nxe2x88x92 region (or pxe2x88x92 region) that is an electric field relaxation region overlaps with an end portion of a gate electrode, and therefore, the invention relating to the GOLD structure TFT is substantially disclosed.
In JP 2001-281704A, there is disclosed a method of manufacturing a GOLD structure TFT, including forming a gate electrode with a laminate structure of two layers and performing a dry etching process consisting of a large number of process steps comprising taper etching and anisotropic etching.
In JP 7-226518A, there is disclosed the invention in which: a film formed of a material constituting a gate electrode is formed; a mask is formed on the film formed of a material constituting the gate electrode; side etching is performed to the film formed of a material constituting the gate electrode to form a gate electrode having a smaller width than that of the mask; and an impurity is introduced into a semiconductor film to form an LDD region.
The development of the GOLD structure TFT excellent in hot-carrier resistance is being progressed in out company as well, and the structure of a typical GOLD structure TFT is described below with reference to FIGS. 3A and 3B. FIG. 3A is a sectional view of a GOLD structure TFT only having the Lov region. FIG. 3B is a sectional view of a GOLD structure TFT having both an Lov region and an Loff region. Note that, in this specification, an electric field relaxation region that overlaps with a gate electrode is referred to as an Lov region, and an electric field relaxation region that does not overlap with a gate electrode is referred to as an Loff region.
In the structure of the GOLD structure TFT only having an Lov region (FIG. 3A), on a transparent insulating substrate 301, an island-like semiconductor layer 302, a gate insulating film 303, and a gate electrode 304 are laminated from the side closer to the substrate 301, and a source region 305 and a drain region 306 are formed in the island-like semiconductor layer 302 outside the gate electrode 304. The above GOLD structure TFT is characterized in that: the gate electrode 304 is constituted of a first-layer gate electrode 304a and a second-layer gate electrode 304b; the first-layer gate electrode 304a is formed longer in size in a channel direction than the second-layer gate electrode 304b; electric field relaxation regions, that is, Lov regions 307 are formed in the island-like semiconductor layer 302 corresponding to the regions of the first-layer gate electrode 304a which are exposed from the second-layer gate electrode 304b; and the source region 305 and the drain region 306 are formed in the island-like semiconductor layer 302 corresponding to the outside of the gate electrode 304.
In the GOLD structure TFT with the above structure, the Lov region 307 is an electric field relaxation region formed so as to overlap with an end portion of the first-layer gate electrode 304a, and consists of an n-type or p-type low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region). The Lov region 307 has a concentration gradient the impurity concentration of which gradually increases toward the source region 305 or the drain region 306 which is an n-type or p-type high concentration impurity region (n+ region or p+ region), and has a characteristic that electric field concentration in a depletion layer in the vicinity of the drain region 306 is further effectively relaxed. The concentration gradient of the Lov region 307 is formed by a method including accelerating an n-type or p-type impurity element in an electric field and making the impurity element pass through a laminate film of the first-layer gate electrode 304a corresponding to the region that is exposed from the second-layer gate electrode 304b and the gate insulating film 303 to be implanted into the island-like semiconductor layer 302 (through-doping method). The formation of the concentration gradient arises from the fact that the first-layer gate electrode 304a (the gate insulating film 303 is irrelevant because it does not change in thickness) which is the upper layer film of the island-like semiconductor layer 302 becomes thinner toward the end portion in implanting the impurity to the island-like semiconductor layer 302 with the through-doping method. Note that, in this specification, a doping method in which an impurity is made to pass through a certain substance layer positioned as the upper layer of an object substance layer to be implanted thereto is referred to as xe2x80x9cthrough-doping methodxe2x80x9d for the sake of convenience.
Further, in the structure of the GOLD structure TFT having both an Lov region and an Loff region (FIG. 3B), on a transparent insulating substrate 401, an island-like semiconductor layer 402, a gate insulating film 403, and a gate electrode 404 are laminated from the side closer to the substrate 401, and a source region 405 and a drain region 406 are formed in the island-like semiconductor layer 402 outside the gate electrode 404. The above GOLD structure TFT is characterized in that: the gate electrode 404 is constituted of a first-layer gate electrode 404a and a second-layer gate electrode 404b; the first-layer gate electrode 404a is formed longer in size in a channel direction than the second-layer gate electrode 404b; first electric field relaxation regions, that is, Lov regions 407 are formed in the island-like semiconductor layer 402 corresponding to the regions of the first-layer gate electrode 404a which are exposed from the second-layer gate electrode 404b; and second electric field relaxation regions, that is, Loff regions 408 and the source region 405 and the drain region 406 are formed in the island-like semiconductor layer 402 corresponding to the outside of the gate electrode 404 so as to be adjacent to each other from the side closer to the gate electrode 404.
In the GOLD structure TFT with the above structure, the Lov region 407 is the first electric field relaxation region formed so as to overlap with an end portion of the first-layer gate electrode 404a, and consists of an n-type or p-type low concentration impurity region (nxe2x88x92xe2x88x92 region or pxe2x88x92xe2x88x92 region). The Lov region 407 has a concentration gradient the impurity concentration of which gradually increases toward the Loff region 408. Further, the Loff region 408 is the second electric field relaxation region formed so as not to overlap with the first-layer gate electrode 404a, and consists of an n-type or p-type low concentration impurity region (nxe2x88x92 region or pxe2x88x92 region). The Loff region 408 has a concentration gradient the impurity concentration of which gradually increases toward the source region 405 or the drain region 406 which is an n-type or p-type high concentration impurity region (n+ region or p+ region). Note that the concentration gradient of the Lov region 407 arises from the fact that the first-layer gate electrode 404a (the gate insulating film 403 is irrelevant because it does not change in thickness) which is the upper layer film of the island-like semiconductor layer 402 becomes thinner toward the end portion in implanting the impurity to the island-like semiconductor layer 402 with the through-doping method. Similarly, the concentration gradient of the Loff region 408 arises from the fact that the gate insulating film 403 that is the upper layer film of the island-like semiconductor layer 402 becomes thinner away from the gate electrode 404.
By the way, the gate electrodes 304, 404 of the GOLD structure TFTs shown in FIGS. 3A and 3B are constituted of the first-layer gate electrodes 304a, 404a and the second-layer gate electrodes 304b, 404b, respectively. The first-layer gate electrodes 304a, 404a are formed longer in size in a channel direction than the second-layer gate electrodes 304b, 404b, respectively. Then, the region of each of the first-layer gate electrodes 304a, 404a which is exposed from each of the second-layer gate electrodes 304b, 404b has a thin tapered shape, and thus, has a thinner thickness toward the end portion. A dry etching method that utilizes high density plasma which is capable of independently controlling a plasma density and a bias voltage applied to a substrate is suitable for processing of the gate electrodes 304, 404 with the above structure. As a specific dry etching method, a dry etching method is known which utilizes a microwave or inductively-coupled-plasma (hereinafter abbreviated to ICP). However, our company employs a dry etching apparatus of an ICP system. This is because the ICP dry etching apparatus enables easy control of plasma, and thus, has an advantage that a larger-scale processing substrate can be easily realized.
In the case where the gate electrodes 304, 404 are processed using the ICP dry etching apparatus, it is necessary to perform a dry etching process consisting of a large number of process steps in combination of taper etching and anisotropic etching. Here, in one process step, an etching process is performed under predetermined etching conditions. Note that the etching conditions mentioned here indicate a chamber pressure, an ICP power density, a bias power density, and a flow ratio of gases constituting etching gas.
For example, in the dry etching step of the gate electrode 304 of the GOLD structure TFT only having an Lov region (see FIG. 3A), the dry etching process consisting of three steps is performed, and thus, a changeover of the etching gas needs to be performed twice. The changeover of the etching gas requires a time until the pressure of an etching chamber is stabilized at the time of the changeover, which leads to the problem of reduction in throughput of the dry etching step. Moreover, there is required the etching gas that is flown until the pressure of the etching chamber is stabilized. Thus, there is also the problem of rise of the process cost due to consumption amount increase of the etching gas. Furthermore, in addition to the above problems, the complication of the dry etching step leads to the process defect and the increase of the number of troubles, and also involves the problem of reduction of yield of a semiconductor device.
Note that the above problems are not limited to the manufacturing steps of the GOLD structure TFT, and are found in the manufacturing steps of the LDD structure TFT as well. This is because the gate electrode is processed through the same dry etching step in either the GOLD structure TFT or the LDD structure TFT.
The present invention has been made in order to solve the above-mentioned problems in the prior art, and therefore has an object to provide a semiconductor device manufactured by applying a dry etching method including a small number of process steps for processing of a gate electrode and a method of manufacturing the semiconductor device. Note that the semiconductor device in this specification indicates semiconductor devices in general the circuit of which is configured by semiconductor devices including a TFT with a GOLD structure. For example, semiconductor display devices such as an active matrix liquid crystal display device and an organic EL display device are included in the category of the semiconductor device.
[Examination of Reduction of the Number of Process Steps in Dry Etching Step]
(Structure of ICP Dry Etching Apparatus)
An ICP dry etching apparatus used in this examination will be explained below. The ICP dry etching apparatus adopts a method in which a high frequency power is applied to a portion consisting of a plurality of spiral coils through an impedance matching device as a means for conducting a plasma process with high precision to thereby produce plasma. Here, the length of a coil is set to one fourth of a high frequency wavelength, and also, a high frequency power is independently applied to a lower electrode that holds an object to be processed, to thereby be applied with a bias voltage. Note that the details of the ICP plasma etching apparatus concerned are disclosed in JP 9-293600A.
FIGS. 4A and 4B are schematic diagrams of the ICP dry etching apparatus concerned. An antenna coil 502 is arranged on a quartz plate 501 provided above a reaction space, and is connected to a first high frequency power source 504 through a matching box 503. The first high frequency power source 504 supplies a high frequency power of 6 to 60 MHz, typically 13.56 MHz. Further, a lower electrode 506 that holds a substrate 505 as an object to be processed is connected to a second high frequency power source 508 through a matching box 507. The second high frequency power source 508 supplies a high frequency power of 100 KHz to 60 MHz, for example, 6 to 29 MHz. When the high frequency power is applied to the antenna coil 502, a high frequency current J flows to the antenna coil 502 in a xcex8 direction, a magnetic field B (Formula 1) is generated in a Z direction, and an induction field E (Formula 2) is generated in the xcex8 direction in accordance with the law of electromagnetic induction of Faraday (see FIG. 4A).
xcexc0J=rot Bxe2x80x83xe2x80x83[Formula 1]                              -                                    ∂              B                                      ∂              t                                      =        rotE                            [                  Formula          ⁢                      xe2x80x83                    ⁢          2                ]            
Electrons are accelerated in the xcex8 direction to collide with gas molecules in the induction filed E, thereby producing plasma. Since the direction of the induction field E is the xcex8 direction, the probability that charged particles collide with an inner wall of a reaction chamber and the substrate 505 to lose energy is small. Further, the magnetic field B hardly affects the portion below the antenna coil 502, and thus, a high density plasma region that is expanded in a flat plate shape is produced. Then, the high frequency power applied to the lower electrode 506 is adjusted, whereby the plasma density and the bias voltage applied to the substrate 505 can be independently controlled. Further, the frequency of the high frequency power to be applied can be changed in accordance with a substance to be etched.
In order to generate high density plasma with the ICP system, the high frequency current J that flows through the antenna coil needs to be flown at a low loss, and the inductance needs to be lowered. In view of this point, a method in which the antenna coil is divided is effective. FIG. 4B is a schematic diagram showing such a structure. A portion consisting of a plurality of spiral coils 510 is arranged on a quartz substrate 509, and is connected to a first high frequency power source 512 through a matching box 511. In this case, when the length of one coil is set to an integral multiple of xc2xc of a high frequency wavelength, a standing wave occurs in the coil portion, and a peak value of the generated voltage can be increased.
A dry etching step that is a processing step of the gate electrode of the GOLD structure TFT is performed by using the ICP dry etching apparatus with the above structure, but there is a problem in that the dry etching step includes a large number of process steps. Thus, the reduction of the number of process steps is examined.
(Substrate Structure and Etching Gas)
First, the structure of a substrate used in this examination will be described. The substrate used here has a structure in which, on a square glass substrate (regular square 12.5 cm on a side) such as a Corning 1737 substrate, a silicon oxide film with a thickness of 200 nm, a TaN film with a thickness of 30 nm, and a W film with a thickness of 370 nm are laminated in order from the side closer to the substrate. Briefly, there is used a substrate with the structure written in the W film (thickness of 370 nm)/TaN film (thickness of 30 nm)/silicon oxide film (thickness of 200 nm)/glass substrate. In the substrate with the above structure, a metallic laminate film with a two-layer structure consisting of the W film (thickness of 370 nm)/TaN film (thickness of 30 nm), which is laminated on the silicon oxide film with a thickness of 200 nm, corresponds to substances to be etched. Note that, as to the examination of an etching rate of each film, there is used a substrate in which a single layer film comprised of the W film (thickness of 370 nm), TaN film (thickness of 30 nm), or silicon oxide film (thickness of 200 nm) is deposited on the glass substrate.
By using the substrate with the above structure, the metallic laminate film consisting of the W film (thickness of 370 nm)/TaN film (thickness of 30 nm) is subjected to a dry etching process using a resist pattern with a thickness of 1.5 xcexcm as a mask. In the prior art, the dry etching process consisting of a large number of process steps comprised of taper etching and anisotropic etching is performed, a mixed gas of CF4, Cl2, and O2 is used in the process step of taper etching, and a mixed gas of SF6, Cl2, and O2 is used in the process step of anisotropic etching. In this examination, the etching gas to be used is limited to the mixed gas of SF6, Cl2, and O2, and the examination of the reduction of the number of process steps is made. Note that, a fluorine-based gas is standardized to SF6 from CF4 in the etching gas comprised of a mixed gas because the increase of the etching rate of the W film (thickness of 370 nm) and the following improvement of the selection ratio of the W film to the silicon oxide film (thickness of 200 nm) can be expected by increasing an existence ratio of a fluoride element.
Note that, hereinafter, description will be made using SF6 as the gluorine-based gas from the above-mentioned reason, but the present invention is not limited to this. SF6 is the most preferable but other fluorine-based gas (for example, CF4) may also be used. Further, a Cl-based gas may be used instead of Cl2.
In this specification, the metallic laminate film is described with the laminate structure of the combination of the W film and the TaN film, but the present invention is not limited to this. The combination of the W film and the TaN film is the most preferable. However, a metal compound containing W as a main constituent or WN (tungsten nitride) may be used instead of W, and Ta may be used instead of TaN.
(Experiment 1)
An evaluation was made on ICP power dependence of an etching rate of each of the W film, TaN film, and silicon oxide film using the ICP dry etching apparatus, substrate, and etching gas which are mentioned above. As to the etching conditions except the ICP power, the gas flow rates of SF6 and Cl2, which correspond to the etching gas, are 40 sccm and 20 sccm, respectively (In this case, the gas flow rate of O2 is 0 sccm.), the chamber pressure is 1.3 Pa, and the bias power is 20 W (bias power density: 0.128 W/cm2). Under the above conditions, an experiment was made with respect to 500 W (ICP power density: 1.019 W/cm2), 700 W (ICP power density: 1.427 W/cm2), and 900 W (ICP power density: 1.834 W/cm2) in ICP power. Note that the bias power indicates the power applied to the substrate 505 from the second high frequency power source 508, and the bias power density indicates a value obtained by dividing the bias power by the area of the substrate 505 (regular square 12.5 cm on a side). Further, the ICP power indicates the power applied to the portion consisting of a plurality of spiral coils 510 from the first high frequency power source 512, and the ICP power density indicates a value obtained by dividing the ICP power by the area of the portion consisting of a plurality of spiral coils 510 (circular region with a diameter of 25 cm) (see FIGS. 4A and 4B).
The results of this experiment are shown in FIGS. 5A and 5B. As understood from FIG. 5A, it was found that, along with the increase of the ICP power, while the etching rates of the TaN film and the silicon oxide film were hardly increased, the etching rate of the W film was increased. FIG. 5B shows the results of the evaluation of the selection ratios of the W film to the TaN film and to the silicon oxide film based on the results of the etching rates. As understood from FIG. 5B, the rise of the selection ratio of the W film to the TaN film and the rise of the selection ratio of the W film to the silicon oxide film are found due to the increase of the ICP power. From the results of this experiment, it is found that the increase of the ICP power is preferable from the viewpoint of the etching rate and the selection ratio of the W film. However, the ICP power of the dry etching apparatus has the maximum value of 1 kW, and a load applied to the dry etching apparatus is concerned when the apparatus is used with the ICP power of about 1 kW. Therefore, the results of this experiment and the load applied to the dry etching apparatus are compared and considered, and as a result, it is judged that an ICP power of about 700 W is suitable.
(Experiment 2)
Next, in the state in which the gas flow rates of SF6 and Cl2 which correspond to the etching gas and the total gas flow rate are fixed to SF6: Cl2=2:1 and 60 sccm, respectively, an evaluation is made on the oxygen addition amount dependence of the respective etching rates of the W film, the TaN film, and the silicon oxide film with the addition amount of oxygen (O2) gas being changed from 0 to 60%. As to the etching conditions except the gas flow rate, the chamber pressure is 1.3 Pa, and the bias power is 10 W (bias power density: 0.064 W/cm2). Then, under the condition of the ICP power of 500 W (ICP power density: 1.019 W/cm2), the evaluation of the etching rates was made with the oxygen addition amount being changed to 20, 40, and 60%. At the same time, an evaluation is made on the case where the ICP power is 700 W (ICP power density: 1.427 W/cm2) and the oxygen addition amount is 40%. Note that Table 1 shows the details of the dry etching conditions of this experiment for reference.
FIGS. 6A and 6B show results of this experiment. As understood from FIG. 6A, it is found that, in the case of an ICP power of 500 W, the etching rate of the W film becomes maximum when the oxygen addition amount is 40%. On the other hand, there is found a tendency that the etching rate of the TaN film lowers along with the increase of the oxygen addition amount. Further, as to the etching rate of the silicon oxide film, there is found no particular tendency except the point that the etching rate lowers when the oxygen addition amount is 0%. FIG. 6B shows the result of the evaluation of the selection ratios of the W film to the TaN film and to the silicon oxide film based on the results of the etching rates. As understood from FIG. 6B, there is found a tendency that the selection ratio of the W film to the TaN film increases along with the increase of the oxygen addition amount. Further, there is found a tendency that the selection ratio of the W film to the silicon oxide film contrary lowers. It is considered that an ICP power of about 700 W is suitable from the results of FIGS. 5A and 5B, and that the oxygen addition amount of 40% is the most suitable from the results of this experiment (FIGS. 6A and 6B). Thus, the etching rate and the selection ratio are similarly evaluated with respect to the case of the ICP power of 700 W and the oxygen addition amount of 40%, and the results are shown in the right ends of FIGS. 6A and 6B. From the results concerned, under the etching conditions of: respective gas flow rates of SF6, Cl2, and O2 as etching gas of 24, 12, and 24 sccm (corresponding to the oxygen addition amount of 40%), a chamber pressure of 1.3 Pa, an ICP power of 700 W, and a bias power of 10 W, the etching rate of the W film of 227 nm, the etching rate of the TaN film of 32 nm, and the etching rate of the silicon oxide film of 34 nm can be obtained, and the selection ratio of the W film to the TaN film of 7.1 and the selection ratio of the W film to the silicon oxide film of 6.8 can be obtained.
(Experiment 3)
Dry etching conditions are set to the following conditions in Table 2. Then, a substrate with the structure consisting of a W film (thickness of 370 nm)/silicon oxide film (thickness of 200 nm)/glass substrate and a substrate with the structure consisting of a W film (thickness of 370 nm)/TaN film (thickness of 30 nm)/silicon oxide film (thickness of 200 nm)/glass substrate are each subjected to a dry etching process using a resist pattern with a thickness of 1.5 xcexcm as a mask.
FIG. 7A shows an SEM photograph in the case where the dry etching process is performed to the substrate with the structure consisting of a W film (thickness of 370 nm)/silicon oxide film (thickness of 200 nm)/glass substrate, and also in the case where over etching is performed from the end point of etching of the W film for about 20 seconds. As understood from FIG. 7A, it is found that the W film has undergone side etching by about 0.2 to 0.3 xcexcm in the state in which the silicon oxide film, which is a base film of the W film, is exposed. Further, FIG. 7B shows an SEM photograph in the case where the dry etching process is performed to the substrate with the structure consisting of a W film (thickness of 370 nm)/TaN film (thickness of 30 nm)/silicon oxide film (thickness of 200 nm)/glass substrate, and also in the case where over etching is performed from the end point of etching of the W film for about 30 seconds. As understood from FIG. 7B, it is not found that the W film has undergone side etching in the state in which the TaN film, which is a base film of the W film, is exposed. From the above, it is understood that there is a causal relationship between side etching of the W film and the exposure of the silicon oxide film in over etching. In the case where the silicon oxide film is exposed in over etching, oxygen emission from the silicon oxide film is considered, and the existence of the emitted oxygen is considered to be a direct cause of side etching of the W film. Taking this point into consideration, the dry etching process is performed to the substrate with the structure consisting of a W film (thickness of 370 nm)/TaN film (thickness of 30 nm)/silicon oxide film (thickness of 200 nm)/glass substrate, and over etching is performed from the end point of etching of the TaN film for a predetermined time. As a result, as shown in an SEM photograph of FIG. 7C, an etching shape with side etching of about 0.2 to 0.3 xcexcm can be obtained in the W film in the state in which the silicon oxide film, which is the base film of the TaN film, is exposed. Further, it is confirmed that the region of the TaN film which is exposed from the W film gradually becomes thinner toward the end portion.
(Construction of Process Step Reduction Process)
It is considered that a metal laminate pattern consisting of the W film/TaN film in which the W film has undergone side etching, which is shown in the SEM photograph of FIG. 7C, can be applied to the gate electrode of the GOLD structure TFT (also including the LDD structure TFT). This is because the gate electrode of the GOLD structure TFT (also including the LDD structure TFT) developed by our company is characterized in that: it is constituted of the TaN film as the first-layer gate electrode and the W film as the second-layer gate electrode; the first-layer gate electrode (TaN film) is larger in channel direction size than the second-layer gate electrode (W film); and the region of the first-layer gate electrode which is exposed from the second-layer gate electrode becomes thinner toward the end portion, and because the gate electrode has substantially the same shape as the metal laminate pattern in FIG. 7C. Therefore, it is considered that the gate electrode of the GOLD structure TFT (also including the LDD structure TFT) can be formed by a one-step dry etching process under the dry etching conditions for a one-step process in Table 2. The substrate sectional views showing the dry etching process in this case are shown in FIGS. 1A and 1B.
Here, the one-step dry etching process indicates that an etching process is conducted once under predetermined etching conditions, and the etching conditions indicate a chamber pressure, an ICP power density, a bias power density, and a flow rate of respective gases constituting etching gas. Further, the dry etching conditions for the one-step process in Table 2 show preferable values, and thus, the present invention is not limited to these values.
The substrate sectional view of FIG. 1A shows the first half of the one-step dry etching process, in which a second-layer gate electrode 105 comprised of a W film and a first-layer gate electrode 106 comprised of a TaN film are subjected to anisotropic etching with a resist pattern 104 as a mask. In this case, the resist pattern 104 is slightly retreated from end portions of the initial resist pattern due to etching, a gate insulating film 103 that is a base silicon oxide film is exposed, and the reduction in thickness progresses in the region outside the end portions of the initial resist pattern. Note that the gate insulating film 103 corresponding to the region inside the end portion of the initial resist pattern is formed into a tapered shape along with the retreat of the end portion of the resist pattern 104 due to etching, and becomes thinner away from an end portion of the first-layer gate electrode 106. Further, FIG. 1B shows a substrate sectional view in the latter half of the dry etching process, in which reduction in thickness of the silicon oxide film that is a base gate insulating film 109 is further progressed as a whole, and side etching of the W film that is a second-layer gate electrode 107 is progressed with an influence of oxygen emitted from the silicon oxide film. In this case, the region of a first-layer gate electrode 108 which is exposed from the second-layer gate electrode 107 is etched into a tapered shape, and becomes thinner toward the end portion. Further, the gate insulating film 109 corresponding to the region inside the end portion of the initial resist pattern is entirely thinned while maintaining the same tapered shape as that in the first half step of the dry etching process.
Note that the silicon oxide film is used as the gate insulating film here, and is the most preferable one. However, the present invention is not limited to this. As described above, it is considered that the silicon oxide film is exposed in over etching, and that oxygen emitted from the silicon oxide film causes side etching of the W film. Therefore, it is considered that the same effect can be obtained with a film other than the silicon oxide film as long as the film is an oxide film.
Further, it is expected that side etching of the W film, which is the second-layer gate electrode, can be promoted without exposure of the base silicon oxide film by increasing the oxygen addition amount based on the findings of the dry etching conditions of the above one-step process. Thus, the dry etching process was performed for a predetermined time under the dry etching conditions in which the oxygen addition amount is increased from 24 sccm to 30 sccm. FIG. 2A is a sectional view showing a substrate after the dry etching process, in which isotropic etching can be performed to a W film that is a second-layer gate electrode 205a in the state in which a TaN film 206 remains. In this case, an end portion of the resist pattern 204a is retreated from the initial resist pattern end portion due to etching, whereby etching proceeds in the TaN film 206 such that the region inside the initial resist pattern end portion has a tapered shape. The TaN film 206 becomes thinner away from an end portion of the second-layer gate electrode (W film) 205a, and thus, has a given residual film thickness in the region outside the initial resist pattern end portion. FIG. 2B is a substrate sectional view after the dry etching process for a predetermined time under the dry etching conditions of a gas flow rate of Cl2, which is etching gas, of 60 sccm, a chamber pressure of 1.0 Pa, an ICP power of 350 W (ICP power density: 0.713 W/cm2), and a bias power of 20 W (bias power density: 0.128 W/cm2), which is performed for anisotropic etching to the TaN film 206. At this time, a first-layer gate electrode 207 formed through anisotropic etching of the TaN film 206 gradually becomes thinner away from an end portion of a second-layer gate electrode (W film) 205b, and suddenly comes to the end at an end portion thereof due to the combination of taper etching and anisotropic etching. Further, etching proceeds in a gate insulating film 208 comprised of a silicon oxide film such that the region inside the initial resist pattern end portion has a tapered shape. The gate insulating film 208 becomes thinner away from the end portion of the first-layer gate electrode 207, and thus, has a given residual film thickness in the region outside the initial resist pattern end portion (refer to FIG. 2B).
From the above results, it is considered that the two-step dry etching process conditions can be applied to the dry etching step of the gate electrode of the GOLD structure TFT (also including the LDD structure TFT). The details of the two-step dry etching process conditions are described in Table 3.
Here, the two-step dry etching process indicates that a dry etching process for the first step is performed under predetermined etching conditions, and a dry etching process for the second step is performed under predetermined etching conditions different from those in the first step. Note that the two-step dry etching process conditions in Table 3 show preferable values, but the present invention is not limited to these values.
From the above results, the substrate with the structure consisting of a W film (thickness of 370 nm)/TaN film (thickness of 30 nm)/silicon oxide film (thickness of 200 nm)/glass substrate is subjected to the dry etching process under the one-step dry etching process conditions (see Table 2) or the two-step dry etching process conditions (see Table 3), whereby the gate electrode of the GOLD structure TFT (also including the LDD structure TFT) can be processed. Therefore, the dry etching process is performed under the one-step dry etching process conditions or the two-step dry etching process conditions, whereby it is considered that the problems in the prior art in the processing step of the gate electrode of the GOLD structure TFT (also including the LDD structure TFT) can be solved.
[Semiconductor Device and Method of Manufacturing the Same]
Description will be made of the structure of the invention relating to a semiconductor device and a method of manufacturing the same in the case where the dry etching process consisting of one step or two steps is applied to the dry etching process of the gate electrode of the GOLD structure TFT (also including the LDD structure TFT).
(Structure of the Invention Relating to Semiconductor Device)
The structure of the present invention relating to the semiconductor device relates to the semiconductor device the circuit of which is configured by a plurality of TFTs including a GOLD structure TFT formed on a principal surface of a transparent insulating substrate, the GOLD structure TFT being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to the transparent insulating substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode that is shorter in size in a channel direction than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to gradually become thinner toward the end portion thereof; a first impurity region having one conductivity is formed in the semiconductor layer corresponding to the region of the first-layer gate electrode which is exposed from the second-layer gate electrode; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that: a dry etching process consisting of one step or two steps is applied to the formation of the gate electrode; the second-layer gate electrode is formed by isotropic etching through the dry etching process; and the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed by taper etching through the dry etching process.
In the structure of the above invention, the transparent insulating substrate may be any one as long as it is a transparent substrate having insulating property. For example, a glass substrate or a quartz substrate may be used. Further, the semiconductor layer indicates an island-like semiconductor layer functioning as an active layer of a TFT, and includes a polycrystalline silicon film having semiconductor characteristics or a crystalline silicon film formed through crystallization by utilizing a catalytic element. The thickness range of the polycrystalline silicon film or crystalline silicon film is suitably about 20 to 200 nm, more preferably about 30 to 70 nm. Note that, in this specification, the polycrystalline silicon film formed by utilizing a catalytic element is referred to as a crystalline silicon film in order to distinguish it from a general polycrystalline silicon film. Here, the reason why xe2x80x9ccrystallinexe2x80x9d is used for the silicon film instead of xe2x80x9cpolycrystallinexe2x80x9d is that since the crystalline silicon film has characteristics that the crystal grains are orientated in substantially the same direction and that it has a high field-effect mobility in comparison with the general polycrystalline silicon film, the crystalline silicon film is distinguished from the general polycrystalline silicon film.
Further, in the structure of the above invention, the gate insulating film is comprised of a silicon oxide film or a silicon oxynitride film, and has a tapered shape so as to be thinner away from the end portion of the gate electrode at a given distance from the end portion of the gate electrode. Note that the thickness of the gate insulating film at the film deposition is suitably about 30 to 200 nm, more preferably about 80 to 130 nm. The reason why the thickness of about 80 to 130 nm is preferable is that a thickness of 80 nm or more is required in order to prevent electrical characteristics of a TFT from being affected due to a stress from the upper layer gate electrode (laminate gate electrode of W film/TaN film).
Further, in the structure of the above invention, the gate electrode is constituted of the first-layer gate electrode comprised of a TaN film with a thickness of about 5 to 50 nm, preferably about 20 to 40 nm and the second-layer gate electrode comprised of a W film with a thickness of about 200 to 600 nm, preferably about 300 to 500 nm, more preferably about 350 to 500 nm. The first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to gradually become thinner toward the end portion thereof. Note that the thickness range of the TaN film is determined in accordance with a good balance between controllability of the thickness in the tapered shape region in dry etching and implantation characteristics in implantation of an impurity element through the TaN film with a through-doping method. Further, the thickness range of the W film is determined by a good balance between prevention of a channeling phenomenon of the W film in implantation of an impurity element and electric resistance of the W film. The channeling phenomenon is a phenomenon in which part of implantation ions enter the semiconductor layer in the lower portion without colliding with W atoms. It is known that a thickness of at least 340 nm or more is required in order to prevent the channeling phenomenon.
Further, in the structure of the above invention, the first impurity region indicates a low concentration impurity region having n-type or p-type conductivity (nxe2x88x92 region, pxe2x88x92 region), and functions as an electric field relaxation region for relaxing an electric field in a channel horizontal direction. Further, the second impurity region indicates a high concentration impurity region having the same conductivity as the first impurity region (n+ region, p+ region), and functions as a source region or a drain region. Note that the first impurity region has a concentration gradient the impurity concentration of which gradually increases away from an end portion of the second-layer gate electrode. Further, the second impurity region has a concentration gradient in a region at a given distance from the end portion of the first-layer gate electrode, and the impurity concentration gradually increases away from the end portion of the first-layer gate electrode.
According to the invention structured as described above, the gate electrode of the semiconductor device the circuit of which is configured by a plurality of TFTs including the GOLD structure TFT can be processed by the dry etching process consisting of one step or two steps. Accordingly, there can be solved the problems in the prior art in the dry etching process, that is, reduction in throughput of the dry etching process, rise of the process cost that follows consumption amount increase of etching gas, and further, reduction of yield of a semiconductor device which follows complication of the dry etching process.
(Structure of the Invention Relating to Method of Manufacturing Semiconductor Device)
The structure of the present invention relating to a method of manufacturing a semiconductor device relates to a method of manufacturing a semiconductor device, including: a first step of forming a semiconductor layer on a principal surface of a transparent insulating substrate; a second step of depositing a gate insulating film to cover the semiconductor layer; a third step of depositing a first-layer gate electrode film on the gate insulating film; a fourth step of depositing a second-layer gate electrode film on the first-layer gate electrode film; a fifth step of forming a resist pattern for formation of a gate electrode; a sixth step of performing a dry etching process to a laminate film constituted of the first-layer gate electrode film and the second-layer gate electrode film to form a gate electrode constituted of a first-layer gate electrode and a second-layer gate electrode shorter in size in a channel direction than the first-layer gate electrode with the resist pattern as a mask; a seventh step of removing the resist pattern; and an eighth step of forming a first impurity region in the semiconductor layer corresponding to the region of the first-layer gate electrode which is exposed from the second-layer gate electrode and at the same time, forming a second impurity region in the semiconductor layer corresponding to the outside of the first-layer gate electrode by implantation of an impurity element having one conductivity, which is characterized in that: the gate electrode is formed by a dry etching process consisting one step or two steps; the second-layer gate electrode is formed by isotropic etching through the dry etching process; and the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed by taper etching through the dry etching process.
In the structure of the above invention, the transparent insulating substrate may be any one as long as it is a transparent substrate having insulating property. For example, a glass substrate or a quartz substrate may be used. Further, the semiconductor layer is an island-like semiconductor layer that functions as an active layer of a TFT, and is comprised of a polycrystalline silicon film or a crystalline silicon film (silicon semiconductor film crystallized by utilizing a catalytic element) having semiconductor characteristics with a thickness of about 20 to 200 nm, preferably about 30 to 70 nm. Further, either a silicon oxide film or a silicon oxynitride film may be applied to the gate insulating film, and the thickness range is suitably about 30 to 200 nm, more preferably about 80 to 130 nm. Further, a TaN film with a thickness of about 5 to 50 nm, preferably about 20 to 40 nm is applied to the first-layer gate electrode film, and a W film with a thickness of about 200 to 600 nm, preferably about 300 to 500 nm, more preferably about 350 to 500 nm is applied to the second-layer gate electrode film.
Further, in the structure of the above invention, a metallic laminate film constituted of the first-layer gate electrode film and the second-layer gate electrode film is subjected to a dry etching process consisting of one step or two steps with the resist pattern as a mask, thereby forming the gate electrode. In this case, since the second-layer gate electrode is formed by isotropic dry etching, the second-layer gate electrode is shorter in size in a channel direction than the fist-layer gate electrode. Further, the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be gradually thinner toward the end portion by taper etching. Further, a dry etching method with the use of high density plasma, which is capable of independently controlling a plasma density and a bias voltage applied to a subject substrate, is appropriate for the dry etching process, and for example, an ICP dry etching apparatus is suitable.
Specific dry etching conditions of the ICP dry etching apparatus are the dry etching conditions described in Tables 2 and 3 as standards. The dry etching conditions in Tables 2 and 3 correspond to a square substrate 12.5 cm on a side. It is considered that, in the case of the actual large-scale square substrate, for example, a large-scale substrate about 1 m on a side, a gas flow rate of etching gas greatly differs along with the increase of the volume in an etching chamber. Therefore, a regulation needs to be placed on not a gas flow rate but a gas flow ratio in order to provide the dry etching conditions with versatility. Further, it is considered that respective parameters in the dry etching conditions slightly change when a different apparatus is used even if it is the same model ICP dry etching apparatus. Moreover, the dry etching conditions need to be regulated in consideration of a degree of room in process in the dry etching process. In view of the above points, a numerical range needs to be introduced for each parameter in the dry etching conditions, and Tables 4 and 5 show the dry etching conditions in which the numerical range is introduced for each parameter. Here, Table 4 corresponds to the dry etching conditions adapted for a one-step process, and Table 5 corresponds to the dry etching conditions adapted for a two-step process. An etching process may be performed with a predetermined value in the numerical range shown in Table 4 or Table 5. Note that, in Tables 4 and 5, parameters of a gas flow ratio, an ICP power density, and a bias power density are regulated with the purpose of avoiding the influence of a substrate size of a subject substrate.
Further, in the structure of the above invention, as to the impurity element having one conductivity, an n-type impurity typified by a phosphorous element may be implanted, or a p-type impurity typified by a boron element may be implanted. Through implantation of the above impurity elements, the first impurity region is formed in the semiconductor layer corresponding to the region of the first-layer gate electrode which is exposed from the second-layer gate electrode by a through-doping method, and at the same time, the second impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode by the through-doping method. At this time, since the impurity regions are simultaneously formed by the through-doping method, the impurity concentrations of the first impurity region and the second impurity region are determined depending on an acceleration voltage and a dosage at the time of implantation of the impurity elements and further on the kind and thickness of the upper layer film of each of the impurity regions. For example, in the first impurity region, the first-layer gate electrode constituted of the gate insulating film and the TaN film exists as the upper layer film, an ion blocking ability of the upper layer film is large, and thus, a low concentration impurity region (nxe2x88x92 region, pxe2x88x92 region) having n-type or p-type conductivity is formed. In this case, since the first-layer gate electrode comprised of the TaN film, which is a part of the upper layer film, is formed into a tapered shape by taper etching, the first impurity region is imparted with a concentration gradient the impurity concentration of which gradually increases toward the second impurity region. On the other hand, in the second impurity region, only the gate insulating film exists as the upper layer film, the ion blocking ability of the upper layer film is not so large, and thus, a high concentration impurity region (n+ region, p+ region) having n-type or p-type conductivity is formed. In this case as well, since a tapered shape region exists in a specific region of the gate insulating film that is the upper layer film, the second impurity region is imparted with a concentration gradient in a region at a given distance from the end portion of the first-layer gate electrode. Note that the first impurity region has a function as an electric field relaxation region for relaxing an electric field in a channel horizontal direction, and the second impurity region is formed so as to have a function of a source region or a drain region.
According to the present invention structured as described above, the gate electrode of the semiconductor device the circuit of which is configured by a plurality of TFTs including the GOLD structure TFT can be processed by the dry etching process consisting of one step or two steps. Accordingly, there can be solved the problems in the prior art in the dry etching process, that is, reduction in throughput of the dry etching process, rise of the process cost that follows consumption amount increase of etching gas, and further, reduction of yield of a semiconductor device which follows complication of the dry etching process.
By the way, the structure of the present invention is similar to the disclosed technique in JP 7-202210A described as a known example, but the structure of the invention differs between both the sides in the following basic points. In the disclosed technique in JP 7-202210A, an example of wet etching or a combination of anode oxidization and wet etching is described in a step of forming a second gate electrode shorter in the dimension in a channel direction than a first-layer gate electrode. In this case, in the formation step of the second-layer gate electrode, the region of the first-layer gate electrode which is exposed from the second-layer gate electrode is hardly reduced in thickness, and thus, the formation of the first-layer gate electrode having a rectangular shape is expected. Also, in the sectional view showing a manufacturing step, the rectangular first-layer gate electrode is shown. On the contrary, the structure of the present invention is characterized in that a first-layer gate electrode corresponding to the region exposed from a second-layer gate electrode is formed into a tapered shape so as to be gradually thinner toward the end portion thereof. Thus, a first impurity region that is an electric field relaxation region is imparted with a concentration gradient in implanting an impurity element by a through-doping method. The concentration gradient promotes an electric field relaxing effect of the first impurity region, and is extremely effective in preventing a hot carrier phenomenon. Accordingly, it is considered that matters for invention specification essentially differ between the present invention and the known example.